The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using an analog oscillator producing clock signals whose frequency is proportional to a control voltage.
A prior art generator 10 as shown in FIG. 1 comprises a frequency divider 12, a phase comparator 14, a voltage generator 16 and an oscillator 19 that are series connected. An output OUT of the oscillator 19 is connected to an input of the frequency divider 12. The generator 10 provides a high-frequency clock signal CKHF (f=FHF) as a function of a reference low-frequency signal CKBF (f=FBF).
The frequency divider 12 receives the high-frequency clock signal CKHF and provides a low-frequency signal CKHF_N that is an image of the signal CKHF, with a frequency equal to f=FHF/N. N is an integer whose value is chosen as a function of the desired frequency FHF0 for the high-frequency clock signal CKHF, and of the frequency FBF of the reference signal CKBF used: N=FHF0/FBF.
The phase comparator 14 has a positive input and a negative input. The signals CKHF_N and CKBF are respectively applied to these inputs. When the signals CKHF_N and CKBF are equal to a 1, the phase comparator 14 determines the phase difference between these signals. This is done by comparing the relative position of the trailing edges of the clock signals CKHF_N and CKBF. The comparator then produces two logic control signals UP, DOWN as a function of the result of the comparison.
The signals UP, DOWN have the following characteristics. If a trailing edge of CKBF is detected first (instants t1 and t3 in FIGS. 2a-2d), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase lead over CKHF_N. The comparator 14 then gives an active signal UP which, for example, takes the logic value 1. UP is then deactivated on the next trailing edge of the CKHF_N (instants t2 and t4 in FIGS. 2a-2d).
If a trailing edge of CKHF_N is detected first (instants t5 and t7 in FIGS. 2a-2d), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase delay with respect to CKHF_N. The comparator 14 then gives an active signal DOWN which, for example, takes the logic value 1. DOWN is then deactivated on the next trailing edge of CKBF (instants t6 and t8 in FIGS. 2a-2d). Otherwise, the signals UP and DOWN remain constant, active or inactive as the case may be.
The voltage generator 16 receives the signals UP and DOWN and gives a variable control voltage VCK. The voltage generator 16 comprises a current generator 17 which gives a current ICH from the control signals UP and DOWN. This current ICH has the following characteristics. ICH=+I0 if UP is active, for example, equal to 1. ICH=xe2x88x92I0 if DOWN is active, for example, equal to 1. ICH=0 if UP and DOWN are inactive.
The current ICH is used to charge or discharge a capacitor 18. When ICH=+I0, the capacitor 18 is charged and the voltage VCK at its terminals increases linearly in a slope proportional to I0. Conversely, when ICH=xe2x88x92I0, the capacitor 18 is discharged and the control voltage VCK at its terminals consequently diminishes linearly in a slope proportional to xe2x88x92I0. Naturally, if ICH is zero, the voltage VCK is kept constant.
The variation xcex94VCK of the voltage VCK, in terms of absolute value is given by the relationship xcex94VCK=I0*xcex94T0/C0, where C0 is the capacitance of the capacitor 18 and xcex94T0 is the duration of a pulse of one of the control signals UP or DOWN.
The pulses UP, DOWN have a maximum duration xcex94T0 max when the signal CKHF has a frequency very distant from its borderline value FHF0. This is especially so when the generator 10 is started up. The maximum duration of a pulse UP, DOWN is in the range of the period PBF: xcex94T0 max≈N*PHF0.
The oscillator 19 gives the high-frequency clock signal CKHF, whose frequency FHF is proportional to the control voltage VCK. When the control voltage VCK rises, the frequency FHF of the signal CKHF rises, and vice versa. The oscillator 19 has, for example, a looped chain of inverters, made up of an odd number of identical, series connected inverters. The signal CKHF is produced at an output of the last inverter which is connected to an input of the first inverter of the chain. The period PHF of the signal CKHF obtained is directly proportional to the switching time in the inverters which is itself modulated as a function of the control voltage VCK.
The general functioning of the clock signal generator 10 is as follows. If a trailing edge of CKBF is detected first (instants t1 and t3 in FIGS. 2a-2d), with the signals CKHF_N, CKBF being previously at a 1, CKBF has a phase lead over CKHF_N. It is estimated in this case that the frequency of the CKHF13 N is lower than that of CKBF, namely that the frequency of CKHF is lower than the desired value FHF0=N*FBF. The comparator 14 then gives an active signal UP, the control voltage VCK rises, as does the frequency of the clock signal CKHF. UP is then deactivated on the next trailing edge of CKHF_N (instants t2 and t4 in FIGS. 2a-2d). The duration of the signal UP applied is thus proportional to the phase difference between CKHF_N and CKBF.
Conversely, if a trailing edge of CKHF_N is detected first (instants t5 in t7 in FIGS. 2a-2d), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase delay with respect to CKHF_N. In this case, it is estimated that the frequency of CKHF_N is higher than that of CKBF, namely that the frequency of CKHF is higher than the desired value FHF0=N*FBF. The comparator 14 then gives an active signal DOWN, and the control voltage VCK diminishes as does the frequency of the clock signal CKHF. DOWN is then deactivated on the next trailing edge of CKBF (instants t6 and t8 in FIGS. 2a-2d). The duration of the signal DOWN applied is thus proportional to the phase difference between the signals CKHF_N and CKBF.
When the generator 10 is powered on, the frequency FHF of the signal CKHF is very low. For example, it is equal to the frequency FBF of the reference signal CKBF. The frequency FHF will then vary as a function of the pulses UP, DOWN produced by the phase comparator. The frequency FHF will increase on an average because the pulses UP are more numerous and their duration is greater than that of the pulses DOWN. The frequency FHF will finally converge towards its borderline value FHF0 . The variations xcex94FHF of the frequency FHF are a function of the duration xcex94UP, xcex94DOWN, of the pulses UP, DOWN, which is itself proportional to the phase difference between the signals CKHF_N and CKBF. It may be recalled that the frequency of CKFH_N is equal to FHF/N.
The control voltage VCK must be limited in amplitude so as to have an acceptable value, especially for the elements forming the oscillator 19. When the generator 10 is started up, the frequency FHF is low, the period PHF is large and the duration of the pulses UP, DOWN is also large, i.e., close to its maximum value xcex94VCKmax. xcex94VCKmax is equal to about ICH*N*PHF0/C0. Consequently, to limit the maximum value xcex94VCKmax of the variations in the control voltage VCK, especially when starting, it is necessary to choose a number N that is small or to increase the capacitance C0 of the capacitor C.
If the frequency of the reference signal CKBF is close to the desired frequency FHF0 for the clock signal CKHF, i.e., with N in the range of 10 to 50, it is possible to choose a capacitance C0 that is not excessively large and can be set up in the integrated circuit.
However, if the frequency of the reference signal is low, i.e., far lower than the frequency FHF0 desired for the clock signal CKHF, then the number N must necessarily be large, such as in the range of 200, and the capacitor C must have a high capacitance value to limit the variations xcex94VCK and hence the maximum value of the control voltage VCK. A capacitor of this kind can no longer be integrated.
The overall precision of the generator 10 is also limited. The uncertainty with respect to the signal CKHF is directly proportional to the variation in the control voltage VCK when the frequency FHF is close to its borderline value FHF0 . As shown above, this variation is in the range of xcex94VCK=I0* T0/C0 less than I0*N*PHF/C0.
It would be advantageous to be able to use a very low frequency reference signal, in the range of 10 Hz to 50 kHz for example, particularly for cost reasons. A reference signal of this kind could be obtained from a particularly stable quartz crystal generator (FBF in the range of 32 kHz) or else from a national electrical power system, which provides a signal with a frequency of 50 Hz, for example, that is also stable. Other sources of low-frequency and low-cost reference signals may also be considered.
In view of the foregoing background, an object of the invention is to provide a phase-locked loop type of clock signal generator that produces very high frequency clock signals from very low frequency reference signals.
Another object of the invention is to provide a clock signal generator that is more precise than existing generators, namely a generator that produces a clock signal whose uncertainty with respect to the frequency (or period) is minimized.
These and other objects, advantages and features according to the invention are provided by a generator that produces a clock signal whose frequency depends on a control voltage, with the generator comprising a comparator for comparing the period of the clock signal with a desired period and for providing at least one first control signal as a function of the result of the comparison.
The generator also comprises a sampler to sample the first control signal and produce a first sampled control signal, and a voltage generator to give the variable control voltage as a function of the first sampled control signal. The variation (xcex94VCK) of the control voltage (VCK) is limited by the duration of the first sampled signal.
Thus, with the invention, the duration of application of the first control signal is reduced by the application, to the voltage generator, of only the first sampled control signal, which is the image (in terms of duration) of the first control signal.
Since the duration of the first sampled control signal is far smaller than the duration of the first control signal, it is then possible to diminish the capacitance of the capacitor of the voltage source to the same extent, without increasing the variations in the control voltage, as shall be seen more clearly below. The size of the generator is thus reduced accordingly.
Furthermore, the total time during which the control signal is active remains proportional to the difference between the frequency of the clock signal and the desired frequency. This means that the variations in the frequency of the clock signal can be managed as earlier.
According to one mode of implementation, the sampler comprises a counter to count pulses of a sampling clock signal when it receives a validation signal, and to give a sampled signal when the number of pulses counted reaches a first predefined number M. The counter is reset when it reaches a second predefined number X. The sampler further includes a first logic gate comprising two inputs to which the sampled signal and the first control signal are applied. The first logic gate produces the sampled control signal.
The sampler of the invention has its rate set by the sampling signal, and it produces a sampled signal every X periods of the sampling signal. The capacitance of the capacitor of the voltage generator may be X times smaller than that of the circuit of FIG. 1.
According to another mode of implementation, the comparator comprises a second output to produce a second control signal representing the result of the comparison. The sampler also comprises a second logic gate comprising two inputs to receive the first and second control signals, and an output to produce the validation signal. The sampler also includes a third logic gate comprising two inputs to receive the sampled signal and the second control signal, and one output to produce a second sampled signal.
The sampling signal may be the clock signal. The sampling signal may also be produced by an oscillator. In this case, the period of the sampling signal is chosen to be smaller than that of the clock signal to increase the overall precision of the generator of the invention.